Presently, system level designers who determine a need for a newly defined integrated circuit, for example to integrate a variety of functions into one chip, often use an application specific integrated circuit (ASIC) or system on a chip (SOC) cell based design. In this approach, a library of known functions is provided, and after the functional design of the device is specified by choosing and connecting these standard functions, and proper operation of the resulting circuit is verified using electronic design automation (EDA) tools, the library elements are mapped on to predefined layout cells which contain prefigured elements such as transistors. The cells are chosen with the particular semiconductor process features and parameters in mind and create a process parameterized physical representation of the design. The design flow continues from that point by performing placement and routing of the local and global connections needed to form the completed design using the standard cells. Eventually, after design rule checks, design rule verification, timing analysis, critical path analysis, static and dynamic power analysis, and final modifications to the design, a “tape out” step is formed to produce photomask generation data. This photomask generation data (PG) is then used to create the optical masks used to fabricate the semiconductor device in a photolithographic process at a wafer fabrication facility.
As semiconductor processes advance, device sizes continue to decrease. Present semiconductor production includes 45 nanometer and soon 32 nanometer minimum feature sizes. These process milestones are usually referred to as “technology nodes”. Advances towards 28 nanometer node mass production are underway and expected shortly. The trend to smaller devices and more advanced nodes will no doubt continue.
As the transistor sizes shrink commensurate with the advances in the technology nodes, the device characteristics and performance become dominated by physical layout effects. The devices also exhibit wide performance differences due to semiconductor process variations. Robust designs must anticipate these effects.
In order to control the device process variation sensitivity, semiconductor manufacturers may use a restricted design rule approach (“RDR”). By restricting where certain layers can be formed with respect to the cell boundaries and with respect to the other layers, the process variation sensitivity problem can be reduced. However, this approach produces additional disadvantages. If horizontal polysilicon routing is not available to the routing process, for example, a layer of metal, typically metal layer 2 must be used to connect internal devices together to form a simple function within a cell. This known prior art approach increases the parasitic coupling significantly, thereby slowing down circuit performance. Generally, an area penalty is created when RDR approaches are used. The amount of silicon needed to implement the cells increases as the design rules are restricted.
This additional metal 2 routing within the cells also adversely uses most of the available metal 2 connectivity resource. Also, because the base cells now include metal 2, a routing congestion problem can happen when trying to route intercell connection signals, or power, clock or ground signals, over the cells. The result is a larger (less dense) layout requiring additional silicon area, or requiring the use of additional metal layers to resolve the congestion problems. These solutions to congestion in the cells add to manufacturing costs.
FIG. 1 depicts a very simple plan view of a cell layout with metal spacing rules for a pair of standard cells shown disposed in an ASIC or SOC design 10 that may be obtained using current cell based design approaches. In FIG. 1, only the cell boundaries for the standard cells 11 and layer boundaries 12 are shown. The layer boundaries indicate the area within the standard cell where a conductive layer can be formed. The layer to layer spacing rule for this example is “a”, which is a minimum distance. For example, “a” might be 5 nanometers. In order to ensure that for any placed cells that neighbor another placed cell, the full layer to layer spacing distance “a” is maintained, the cells 11 in this prior art approach are configured so that no portion of the layer is placed outside the area of the layer boundaries 12. Thus, as shown in FIG. 1, when two such cells are packed together as neighbors, a spacing “a” is always maintained. Typically, the conductor layer will be formed of aluminum and its alloys or copper and its alloys, but other conductive layers that are isolated by dielectric may be used. Doped polysilicon is one alternative.
FIG. 2 is a second plan view that further illustrates how two cells are placed with a minimum layer to layer spacing rule “a” in the prior art. Again, the figure illustrates in a very simple plan view two neighboring standard cells 11. Each has two instances of a typical layer 13, for example the layer may be metal 1, which may be formed of aluminum or copper, or it may represent a conductor layer such as polysilicon which may also have a silicided layer as is known in the art. The layers 13 are subject to the minimum spacing rule. The layers 13 are therefore placed so that they are not closer than a distance of a/2 from the boundary of the cell. The cells are a uniform width B which also determines a pitch for the cells. The neighboring cells then cannot be arranged so that the layers 13 (in this example embodiment) are closer than a distance “a” from one to another.
In advanced semiconductor processing, the use of RDRs to improve the yield of the manufactured devices is known. One RDR restriction that may be used at the 32 nanometer node, and probably at smaller technology nodes in the future, is that polysilicon, the lowest conductor layer in the IC fabrication, will be restricted to be placed in a unitary direction. That is, all of the polysilicon conductors may be required to be parallel to one another and running in only the vertical, or only the horizontal, direction. Also, the polysilicon layer may be further restricted to be of a uniform width and pitch. These restrictions insure more uniform results over process variations, that is, the devices manufactured with these restricted layout rules will have less process sensitivity.
However, these restrictions also make connecting library functions in a typical standard cell difficult. FIG. 3 depicts, as a non-limiting and very simple example, a two input NAND gate that may be found in a typical design library as used in IC design and particularly in ASIC design. In FIG. 3, it can be seen from examining the circuit that when both the inputs B and A are at a logical high level, a “1”, both N type transistors N1 and N2 will become conducting. At the same time, both P type transistors P1 and P2 will be non-conducting. Output Y will be coupled to ground, or the supply labeled Vss, and will be a logical “0”. In case either of the inputs B and A are at a logical low level, the path through N2 and N1 will be broken and at least one of the P type transistors will be active. Accordingly, output Y will be coupled to the positive supply of VDD and will be a logical “1” or high level.
As is known in the art, a CMOS standard cell can be formed containing four or more transistors with the P and N gates coupled together to form common elements (CMOS inverters) that may be further coupled using local interconnections to form a wide variety of library elements. This cell layout is then replicated in a cell array and may form a large part of, or all of, a device for implementing the functions specified by a designer using a circuit standard cell library and using known design and verification tools. More complex functions such as ALUs, register files, FIFOs, latches, multipliers, adders, multiplexers, switches and so forth may also be formed by using a plurality of the standard cells coupled together by multiple levels of interconnect. By using known elements that are mapped onto the standard cells in advance, a robust design methodology is produced, the designer does not have to verify that the circuits in the cell library function correctly at the transistor level, as that work was done in advance. Instead, only the functional operation of the interconnected elements has to be verified. Skilled circuit designers with expertise in transistor and device design have already verified that the circuits in the library will work and models of the devices are provided to the tools including drive strengths, delays, and so on, so that the designer of a new ASIC does not have to reinvent transistor, logic or even register level circuitry every time a new device is created.
Further, most ASICs manufactured today may include, in addition to the cells, a plurality of embedded functions. These may include, for example, a microprocessor, RISC processor, analog to digital converter, radio transceiver such as for a mobile telephone or wireless device, or other known function such as a memory module, incorporated with a plurality of user defined logical functions.
The two input NAND gate 30 of FIG. 3 has inputs A and B coupled to a respective pair of CMOS transistors P1 and N1, for input A, and P2 and N2, for input B. Output Y is coupled to the current conduction paths of both P1 and P2, and also to the series current conduction path of the n type transistors N1 and N2. So output Y has three connections inside the NAND gate, while inputs A and B each have 2 connections. Inputs A and B are coupled to gate terminals. Output Y is coupled to the drains of P type transistors P1 and P2, and to the source of transistor N2. Transistor N1 has a current conduction path coupled to ground. Transistors N1 and N2 form a series path to VSS or ground when the two inputs are both high.
FIG. 4 depicts, in a plan view, the layout patterns for two adjacent standard cells 42 and 44 in a layout for a portion of an integrated circuit 40. Each of these two cells has width B. Each cell is connected to form a two input NAND logic gate as shown in FIG. 3. In an actual device, many more standard cells, hundreds, thousands or more of these cells will be placed to implement the circuitry of the integrated circuit.
The standard cells are formed, in this illustrative example, on a P type semiconductor substrate, or alternatively, for silicon-on-insulator (“SOI”), it could be on an epitaxial layer of doped or undoped semiconductor material. P and N type active areas 46 and 26 are formed at the top and bottom of the cells 42 and 44 as shown, respectively. The P type active areas 46 are typically formed in an N type well, using a double diffused process, ion implantation, thermal anneals, and like semiconductor processing steps as are known in the art. The active areas or “oxide dimensioned” (OD) areas 46 and 26 are defined by isolation oxide regions. The isolation regions are also not visible but typically shallow trench isolation (STI) or LOCOS oxidation is used to isolate the active areas one from another. In the standard cell layout of FIG. 4, the active areas take an L shape, although the “L” is not visible in this illustration. This L shape produces some asymmetry or imbalances in the performance of the cell which will be detailed later.
Unidirectional polysilicon (PO) and gate oxide regions 22 and 24 are formed. These include dummy polysilicon vertical lines such as 43 and 41 which do not overlie any active area but form the cell boundary regions. Dummy vertical PO lines may be used for interconnection to form other circuits within the cell. PO lines 22 and 24 are deposited in the usual MOS processing steps of oxide deposition, polysilicon deposition, etch, sidewall formation before or active source and drain diffusion implantation, thermal anneal, etc as are known in the art. Thus, the polysilicon lines 22 and 24 form MOS transistor gates and lie over a gate dielectric (not visible) which may be, for example, an oxide or nitride or oxynitride that forms the gate dielectric. Other high k and low k oxides may be used.
Using conventional processing, source and drain diffused regions (labeled “s” and “d”) are formed adjacent the polysilicon gates. For the P channel transistors P1 and P2 as shown in the figure, P type doping is performed. Typically, a self aligned process is used, that is, the gate polysilicon is used as an alignment mask for these source/drain diffusion steps. Alternative processes are known. Implant, diffusion, anneals and silicide steps may be used as are known in the art. For transistors N1 and N2 as shown in the figure, N-type dopants are used to form source and drain regions on either side of the polysilicon gates.
After an interleaved insulating layer is deposited to prevent electrical shorts between layers, a conductor such as metal 1 is deposited and patterned to connect some of the circuit elements. Vias through these insulating layers may be used to couple the conductor layer metal 1 to the underlying polysilicon PO layers, which are either gate conductors for transistors N1, P1, N2, P2, or dummy polysilicon lines. In FIG. 4, metal 1 portion 34 is coupled to terminal B for connecting one input of the 2 input NAND gate to external circuits, to gates of transistors P2 and N2. Pin A, another input, is coupled by metal portion 32 to the polysilicon gate 22 which forms the gate terminal of transistors P1 and N1. Reference to FIG. 3 will show how this input is coupled to the gate of a P and an N type transistor, which together form one inverter in CMOS logic. Contacts couple conductors to the source and drain diffused regions.
Other connections are also made by the layout of FIG. 4, to complete the NAND gate logic as shown in FIG. 3. Metal 1 bus 28 couples a voltage supply Vss, or ground, to the source of transistor N1. Transistors N1 and N2 share a diffusion region that forms the drain of N1 and the source of N2. Transistor N2 has a drain region that is coupled by a contact to the metal 2 layer for the Y terminal.
Similarly, the metal 1 buss 53 forms a VDD terminal. Buss 53 is coupled horizontally across the ends of the polysilicon PO regions and forms the top of the standard cells. metal 1 is also used to couple VDD to the common drain region for transistors P1 and P2, which is in the center portion between the polysilicon gates in diffusion 46. Sources ‘s’ for transistors P1 and P2 are coupled together by a metal 1 portion 48 through the use of contacts, and to the vertical metal 2 portion 36 to form the Y terminal.
Referring to FIG. 3, it can be seen that the output terminal Y in FIG. 3 is to be coupled to the drain regions of transistors P1 and P2 and the source region of N2
The layout of the two cells in FIG. 4 illustrates some of the disadvantages of the layer to layer, and layer to cell boundary spacing rules of the prior art. Cell boundary 41, for example, is shown and additional cell boundaries are shown in vertical alignment with and running through the dummy polysilicon portions.
In FIG. 4, the use of metal 2 portions is necessary to couple the two input NAND gate elements to complete the logic gate connections in the standard cells 42 and 44. This is so because the pin A and the output pin Y, and connections for Y cannot be routed in metal 1, as there is not sufficient space to place a vertical metal 1 line that meets the “a/2” spacing to the cell boundary. Similarly, input pin A cannot be formed in metal 1, due to the design rule requirement that metal 1 be no closer than a/2 to the cell boundary and must be spaced at least distance “a” from other metal 1 layers. This distance is shown in the figure. Therefore, these connections are necessarily completed using metal 2, such as 36. This implementation disadvantageously increases the parasitic RC load on the layer metal 2, increases routing congestion (by making metal 2 routing for interconnect go around the standard cell areas) and uses up some of the available metal 2 resources, resulting in either the need for additional metal layers and the associated processing costs, or larger silicon area overall to complete the device.
Thus, there is a continuing need for improved methods and layout structures to address these and other problems with the standard cells of the prior art as used in advanced semiconductor processes.